FIG. 1 illustrates a graphics system architecture 10. The graphics system architecture 10 includes a host computer 12 which comprises a CPU 14, a main system memory 16 and a disk memory 18 all interconnected by a system bus 20. The graphics system architecture 10 also includes a graphics subsystem 30. The graphics subsystem 30 includes a graphics processor 40 which is in communication with the system bus 20. The graphics subsystem 30 also includes a local bus 42 to which the graphics processor 40 is connected. A frame memory 50 is connected to the local bus 42. The frame memory 50 stores frame image data generated by the graphics processor 40. A Z-buffer 60 connected to the local bus 42 stores data related to depth of field for use in connection with the display of overlapping windows. The RAMDAC 62 is a digital-to-analog converter which mixes digital data from the frame memory 50 with screen control signals to generate analog signals compatible with the display 64.
The conventional architecture of the frame memory 50 is illustrated in FIG. 2. The frame memory 50 is formed from a plurality of VRAMs. The VRAMs are arranged, in a plurality of banks (e.g., bank 0, bank 1, bank 2, bank 3). Each bank comprises a plurality of buffers, e.g., buffer 0, buffer 1, buffer 2. The frame memory 50 is organized in a plurality of bit planes, e.g., twenty-four bit planes labeled 0, 1, . . . , 23, with eight bit planes in each buffer. Illustratively, the 4n.sup.th pixel of every scanning line of the display 64 (see FIG. 1) is stored in bank 0, the 4n+1.sup.th pixel of every scanning line is stored in bank 1, the 4n+2.sup.th pixel is stored in bank 2 and the 4n+3.sup.th pixel is stored in bank 3.
A true color pixel comprises twenty four bits, with one bit being stored in each bit plane. Illustratively, for a true color pixel in the frame memory 50 of FIG. 2, the R (Red) component occupies bit planes 0-7, the G (Green) component occupies bit plane 8-15, and the B (Blue) component occupies bit planes 16-23. (Instead of an RGB representation, true color pixels may be represented by two chrominance components and one luminance component). Illustratively, the local bus 42 has a width of thirty-two bits so that only one true color pixel can be accessed in (i.e., read from or written into) the frame memory 50 during each cycle. The local bus 42 transmits data in thirty-two bit words, with each bit position being labeled 0, 1, . . . , 31. A word for use on the local bus 42 is illustrated in FIG 3. As shown in FIG. 4, when a true color pixel is transmitted on the bus, the R component occupies bit positions 0-7, the G component occupies bit positions 8-15 and the B component occupies positions 16-23. The positions 23-31 are not used. Thus, there is a one-to-one correspondence between the twenty-four bit planes of the frame memory 50 of FIG. 2 and the first twenty-four bit positions of the data words on the data bus 42. The graphics processor 40 processes true color pixels based on the ordering of the R, G, B components shown in FIG. 4.
In addition to the true color mode, pixels may be also be stored using the index mode. In the index mode, each pixel is represented by 8 bits. The pixels (e.g., four consecutive pixels P1, P2, P3, P4) are conventionally stored in the frame memory 50 in the positions shown in FIG. 5 with consecutive pixels stored in consecutive banks. However, because of the one-to-one correspondence between bit planes in the frame memory and bit positions on the local data bus 42, only one eight bit index mode pixel location in the frame memory can be accessed in a cycle. Four consecutive index mode pixels cannot be accessed in a single cycle. The location of such a single index mode pixel (e.g., the pixel P2) in a data word on the data bus 42 is shown in FIG. 6. As shown in FIG. 6, twenty-four bit positions in the data word are unused. Thus, despite the fewer number of bits per pixel when the index color mode is used, no processing speed advantage is achieved; there is still only one pixel in each data word on the bus 42, i.e., one pixel per cycle.
FIG. 7 shows a prior art solution to this problem. An additional frame memory 80 is added to the frame memory 50. The additional frame memory 80 includes four buffers (buffer 0, buffer 1, buffer 2, buffer 3) and a total of 32 bit planes labeled 0, 1, . . . , 31. The consecutive index pixels P1, P2, P3, P4 each occupy eight bit planes, 0-7, 8-15, 16-23, 24-31, respectively. Because of the one-to-one correspondence between bit planes and bit positions in data words on the bus 42, the pixels P1, P2, P3, P4 may be accessed simultaneously and positioned in a data word on the bus 42 as shown in FIG. 8.
This enables four index color pixels to be processed in each cycle, thereby achieving a significant speed advantage, but the cost is additional memory capacity.
It is an object of the present invention to provide a frame memory architecture which overcomes the problems of the prior art and efficiently processes both true color and index color mode pixels. In particular, it is an object of the present invention, to provide a memory architecture which efficiently processes both true color and index mode pixels in single environment without the use of an additional frame buffer. It is also an object of the invention to provide a memory architecture for processing true color and index mode pixels in a manner which improves the speed and efficiency of the graphics system.